Technology

Trump Pump Goes Thump as Chips Stock Dump

Leslie knorpe! is that you?!

Not to mention that he basically was holding the money already promised to Intel from the chips act hostage until they bribed him with shares.

The dip was also largely trumps fault for with holding money that had already been promised to Intel from the chips act, despite Intel having already spent a bunch of their own money on building new production lines.

It’s to get chip fab in the US. Taiwan is not a stable place for the advanced chips the US and rest of the world rely on.

Imagine the grin after writing that headline!

All the people you condemn have personally gained massive amounts of wealth and lots of Epstein access. Are they the idiots?

…I hate this place.

The Mierdas touch.

The fifth horseman: Bankruptcy

CPUs in the sense of serial compute speed haven't really been advancing nearly as quickly for the past 20 years.

https://www.science.org/doi/full/10.1126/science.aam9744?referrer=https%3A%2F%2Fkagi.com%2F

Over the past 50 years, the miniaturization of semiconductor devices has been at the heart of improvements in computer performance, as was foreseen by physicist Richard Feynman in his 1959 address (1) to the American Physical Society, “There’s Plenty of Room at the Bottom.” Intel founder Gordon Moore (2) observed a steady rate of miniaturization and predicted (3) that the number of transistors per computer chip would double every 2 years—a cadence, called Moore’s law, that has held up considerably well until recently. Moreover, until about 2004, new transistors were not only smaller, they were also faster and more energy efficient (4), providing computers with ever more speed and storage capacity. Moore’s law has driven economic progress ubiquitously.

Unfortunately, Feynman’s “room at the bottom” is no longer plentiful. The International Technology Roadmap for Semiconductors [(5), p. 36] foresees an end to miniaturization, and Intel [(6), p. 14], a leader in microprocessor technology, has acknowledged an end to the Moore cadence. Indeed, Intel produced its 14-nm technology in 2014, but it stalled on producing its 10-nm technology, due in 2016, until 2019 (7). Although other manufacturers continued to miniaturize—for example, with the Samsung Exynos 9825 (8) and the Apple A13 Bionic (9)—they also failed to meet the Moore cadence. There isn’t much more room at the bottom.

Why is miniaturization stalling? It’s stalling because of fundamental physical limits—the physics of materials changes at atomic levels—and because of the economics of chip manufacturing. Although semiconductor technology may be able to produce transistors as small as 2 nm (20 Å), as a practical matter, miniaturization may end around 5 nm because of diminishing returns (10). And even if semiconductor technologists can push things a little further, the cost of doing so rises precipitously as we approach atomic scales (11, 12).

Few industries see exponential improvements for decades on end. Intel did very well when everyone needed a new CPU every few years because things had improved so incredibly much.

Today, we mostly have to settle for improvements in parallelism, and software that can leverage really large gains there has tended to take the GPU route—simple hardware, but designed around much more parallelism.

As we shall see, the primary advantage of hardware streamlining comes from providing additional chip area for more circuitry to operate in parallel. Thus, the greatest benefit accrues to applications that have ample parallelism. Indeed, the performance of hardware for applications without much parallelism has already stagnated. But there is plenty of parallelism in many emerging application domains, such as machine learning, graphics, video and image processing, sensory computing, and signal processing. Computer architects should be able to design streamlined architectures to provide increasing performance for these and other domains for many years after Moore’s law ends.

Hardware that is customized for an application domain can be much more streamlined and use many fewer transistors, enabling applications to run tens to hundreds of times faster (46). Perhaps the best example today is the graphics-processing unit (GPU) [(41), section 4.4], which contains many parallel “lanes” with streamlined processors specialized to computer graphics. GPUs deliver much more performance on graphics computations, even though their clocks are slower, because they can exploit much more parallelism. GPU logic integrated into laptop microprocessors grew from 15 to 25% of chip area in 2010 to more than 40% by 2017 (see Methods), which shows the importance of GPU accelerators. Moreover, according to the Top 500 website, which tracks high-performance computing technology, only about 10% of supercomputers that were added to the Top 500 list in the year 2012 contained accelerators (often GPUs), but by 2017, that share had grown to 38% (12). Hennessy and Patterson (45) foresee a move from general-purpose toward domain-specific architectures that run small compute-intensive kernels of larger systems for tasks such as object recognition or speech understanding. The key requirement is that the most expensive computations in the application domain have plenty of parallelism and locality.

Nvidia is a leader in GPUs, and people are willing to pay a lot for new GPUs, because those are still improving rapidly. Intel is a leader in CPUs, and CPUs aren't.